1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a logic circuit or a memory cell array in which a wiring having a relatively high electrical resistance is formed and a plurality of driving elements or driving circuits and load means are connected to the wiring.
2. Description of Related Art
A conventional logic circuit is, for example, constructed such that a plurality of N-channel insulated gate field effect transistors (hereinafter called "transistors") are connected to nodes of a polycrystalline silicon (hereinafter called "polysilicon") wiring at their drain regions, to a ground potential line at their source regions and to signal lines, from which input (driving) signals are applied, at their gate electrodes, respectively. Between an output terminal and one end node nearest to the output terminal among the nodes of the polysilicon wiring, a sense inverter is formed, and a P-channel transistor as a load element is connected to a line between the one end node and the sense inverter at its drain region, to a power source voltage line (V.sub.DD line) at its source region and to a ground potential line at its gate electrode.
The aforementioned circuit functions as an OR circuit, that is, when the level of any one of the input signals applied to the gate electrodes of the driving transistors becomes "H", meaning the level of the input signal is high, the potential of the end node or the line connected to the end node goes down and thus the level of the output signal at the output terminal becomes "H". The channel width and the channel length of each of the transistors in the circuit is so determined that the potential of the end node, which has gone down due to the driving operation of one of the driving transistors, becomes lower than the threshold value of the sense inverter. The sense inverter functions so that the potential of the end node is changed to the potential of the power source voltage (V.sub.DD) or the ground potential and the resultant voltage is outputted from its output terminal.
The polysilicon wiring has an electrical resistance larger than a metallic wiring, and therefore, unfavorable resistors are inevitably caused in the wiring between respective nodes. In the prior art, however, any load element is not connected at the side of the other end node remoted from the output terminal. Therefore, variation of circuit characteristics by respective driving transistors becomes large and misoperations of the circuit are apt to occur. If a current flowing through the load transistor connected to the output side is of a small value, a high speed operation of the circuit cannot be obtained.